Date of Award
2006
Degree Type
Thesis
Degree Name
Master of Engineering Science
Program
Electrical and Computer Engineering
Supervisor
Dr. Abid
Abstract
As the VLSI industry moves towards nano-scale dimensions, the increasing number of defective devices, due to higher process variations, is becoming problematic. Defect-tolerant designs at the circuit level are required to improve the circuits’ functionality and the manufacturing yield. This thesis proposes new Defect-Tolerant adders and multipliers based on Triple Modular Redundancy (TMR) and Transistor Redundancy.
The majority Voter circuit designs, based on Transistor Redundancy, are proposed. Then, the proposed Adders, incorporating our new voters, show an increase in defect-tolerance compared to conventional TMR Adders but with a small increase in transistor count and time delay.
To reduce the number of transistors and power consumption of TMR designs, efficient signed array and tree multipliers are proposed. The first design replaces AND gates with NAND gates in the partial product generators by using five new types of Full-bit adders. The second design uses conventional architecture but introduce low-area low-power circuit implementations of AND and NAND gates.
Recommended Citation
El-Razouk, Hayssam, "Defect-Tolerant Adders and Multipliers with Transistor Redundancy" (2006). Digitized Theses. 4950.
https://ir.lib.uwo.ca/digitizedtheses/4950