Electronic Thesis and Dissertation Repository

Degree

Master of Engineering Science

Program

Electrical and Computer Engineering

Supervisor

Dr. Gerry Moschopoulos

Abstract

AC-DC power factor correction (PFC) single-stage converters are attractive because of their cost and their simplicity. In these converters, both PFC and power conversion are done at the same time using a single converter that regulates the output. Since they have only a single controller, these converters operate with an intermediate transformer primary-side DC bus voltage that is unregulated and is dependent on the converters’ operating conditions and component values. This means that the DC bus voltage can vary significantly as line and load conditions are changed. Such a variable DC bus voltage makes it difficult to optimally design the converter transformer as well as the DC bus capacitor.

One previously proposed single-stage AC-DC converter, the Single-Stage Buck-Boost Direct Energy Transfer (SSBBDET) converter has a clamping mechanism that can clamp the DC bus voltage to a pre-set limit. The clamping mechanism, however, superimposes a low frequency 120 Hz AC component on the output DC voltage so that some means must be taken to reduce this component. These means, however, make the converter transient slow and sluggish.

The main objective of this thesis is to minimize the 120 Hz output ripple component and to improve the dynamic response of the SSBBDET converter by using a new control scheme. In the thesis, the operation of the SSBBDET converter is reviewed and the proposed control method is introduced and explained in detail. Key design considerations for the design of the converter controller are discussed and the converter’s ability to operate with fixed DC bus voltage, low output ripple and fast dynamic response is confirmed with experimental results obtained from a prototype converter.

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