Rational Interface Design for High-Performance All-Solid-State Lithium Batteries

Changhong Wang, The University of Western Ontario

Abstract

All-solid-state lithium batteries (ASSLBs) have gained substantial attention owing to their excellent safety and high energy density. However, the development of ASSLBs has been hindered by large interfacial resistance originating from the detrimental interfacial reactions, poor solid-solid contact, and lithium dendrite growth. The research in this thesis aims at achieving high-performance ASSLBs via rational interface design and understanding the interfacial reaction mechanisms.

At the cathode interface, an ideal dual core-shell nanostructure was first designed. Moreover, single-crystal LiNi_0.5Mn_0.3Co_0.2O₂ (SC-NMC532) cathode was compared with polycrystalline NMC532, the former exhibits much enhanced Li⁺ diffusion kinetics in ASSLIBs. Besides, it is found that the interfacial structural degradation significantly impedes interfacial Li⁺ transport in ASSLIBs. Fortunately, the interfacial coating is demonstrated to be effective in suppressing interfacial degradation.

Furthermore, the ionic conductivity of interfacial layer LNTO was purposely tuned to investigate the effect of interfacial ionic conductivity on ASSLIBs, it is revealed that enhancing the interfacial ionic conductivity is very crucial for high-performance ASSLBs. The conclusion was confirmed by the in-situ growth of Li₃InCl₆. The high Li⁺-conductive Li₃InCl₆ coated LCO demonstrates an ultra-small interfacial resistance of 0.13 W.cm^-2 and excellent electrochemical performance.

At the anode interface, an inorganic-organic hybrid interlayer and a solid-state plastic crystal electrolyte were successfully engineered to prevent the interfacial reactions and lithium dendrite formation. Last but not least, a solid-liquid hybrid electrolyte was developed as interfacial solid-liquid electrolyte interphase (SLEI) to achieve high-performance ASSLBs.

In summary, the discoveries in this thesis provide important guidance to achieve high-performance ASSLBs via rational interface design.