Electronic Thesis and Dissertation Repository

Thesis Format



Master of Engineering Science


Electrical and Computer Engineering


Dounavis, Anestis


Two computationally efficient and passive interconnect transmission line models which expand upon methodologies currently used in the literature are discussed in this thesis. These approaches can be used to determine how a signal is transferred along wires in applications such as on-chip, PCB, and power line circuits. The first methodology uses a novel decoupling scheme with a Numerical Inverse Laplace Transform (NILT) to solve the far-end time domain voltage solution of large coupled Very Large Scale Integration (VLSI) interconnect structures. This methodology is significantly faster than SPICE simulations at a slight reduction in accuracy. The second methodology uses a modification of the Generalized Method of Characteristics (MoC) approach to solve for the near and far-end voltage and current measurements of single interconnect models. This methodology performs rational approximation fitting on key functions offline to ensure the model is passive by construction as long as certain conditions are ensured.

Summary for Lay Audience

Wires are used to connect two points in an electric circuit in order to transfer the voltage from these two points, referred to as nodes. For ideal wires, these two nodes will have the same voltage and a voltage applied on one end of the wire will instantaneously appear on the other end. Physical wires do not have this characteristic, and in certain situations such as the wires in computer chips or the transmission lines that bring power to our cities, the non-ideal effects are significant and need to be modelled. Voltages take time to travel along the wires and can even affect nearby wires that are not physically connected. Computer chips can have more than a billion transistors acting as switches which quickly turn on and off. Together, with the wires connecting these transistors, is a system which controls our electronic devices. The high switching speeds and proximity of the wires connecting these densely packed chips result in significant differences in the signal on each end of the wire. In addition, nearby wires can also have momentary voltage spikes. This research works to determine and model these effects.

Although the equations which govern these effects are known, the exact solution to these equations is unknown. Therefore, a tool which provides an approximation of these effects, that is both accurate and efficient is important for engineers who need to know how different circuit parameters affect their design. Another important aspect is ensuring that the model is stable. If a model is unstable it can produce results which instead of converging to a voltage measurement, can continually oscillate to unreasonably large values due to an unstable model. Tools which can model these wires are useful for designers of electric circuits, such as VLSI layouts or power grids, and this research develops two of these models.

Available for download on Saturday, November 01, 2025