Date of Award


Degree Type


Degree Name

Doctor of Philosophy


Electrical and Computer Engineering


Dr. Gerasimos Moschopoulos


The dramatic growth in the use of electronic equipment in recent years has resulted in a greater need to ensure that the line current harmonic content of any equipment connected to the ac mains is limited to meet regulatory standards. This requirement is usually satisfied by incorporating some form of Power Factor Correction (PFC) to shape the input phase currents so that they are sinusoidal in nature and are in phase with the input phase voltages. Three-phase PFC can be actively performed using a six-switch converter either to process the bulk of the power fed to the load or to be as an active filter that processes only a portion of the power fed to the load. Using a six-switch converter, however, is costly and complicated given the number of active switches that must be used and the sophisticated control needed to ensure a good power factor. For power converters of 6 kW or less (a range just high enough where three-phase converters are a better option than single-phase converters), cheaper and simpler methods of performing three-phase active input PFC have been developed using converters with less than six switches, such as the three-phase single-switch buck-type converter. The conventional buck-type converter, however, has several drawbacks that have limited its widespread use, including a limited operating range and very high switch voltage stresses. Novel reduced switch three-phase buck-type ac-dc converter topologies are presented in this thesis that overcome the limitations of the conventional three-phase buck converter. In addition, a variable frequency technique that can minimize the switch voltage stresses of buck-type converters is also presented. In this thesis, three reduced-switch ac-dc converters are investigated - a quadratic Pulse Width Modulated (PWM) converter, a new quadratic soft-switched quasiresonant converter with reduced switching frequency operating range, and a new two-switch PWM converter with reduced switch voltage stresses. The steady state behaviors of these converters are discussed and mathematical analysis of their steadystate characteristics is provided. Systematic design procedures are developed for each of the converters and are presented along with the design examples. The feasibility of these converters is confirmed with the experimental results obtained from laboratory prototypes.



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