Master of Engineering Science
Electrical and Computer Engineering
Signal integrity analysis for on-chip interconnect becomes increasingly important in high-speed designs. SPICE, a conventional circuit simulator, can provide accurate prediction for interconnects, however, using SPICE is extremely computationally expensive. On the other hand, explicit moment matching technique can produce unstable poles for highly accurate approximations and implicit moment matching technique can obtain more accurate approximations at the expense of computational complexity. This thesis presents an analytic model to efficiently estimate the signal delays of RLC on-chip interconnects. It uses the numerical inversion of Laplace transform (NILT) to obtain time function, suitable for transient analysis. Since the integration formula of the NILT is numerically stable for higher order approximations, the developed algorithm provides a mechanism to increase the accuracy for delay estimation. Numerical examples are implemented and compared with HSPICE, two-pole model and Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) to illustrate the efficiency and validity of the proposed work.
Summary for Lay Audience
Very-large-scale-integration (VLSI) and integrated circuits (IC) are widely used in such electronic fields such as mobile, satellite communication, computer hardware, microelectromechanical systems, robotics. As the rapid decrease in feature size and significantly increase in circuit complexity, density and operating speeds, applying an accurate and efficient method for analyzing on-chip interconnects becomes very important for circuit designers. The evaluated results generated by analysis methods can provide the exact descriptions for the ability or availability of a high-speed system being designed to function under stated conditions for a specified time period. Due to the improper design, the interconnect effects such as the signal delay, crosstalk, and ringing can severely degrade signal integrity (SI), i.e. a set of measures of the quality of an electrical signal, and cause false actions of the circuits, which brings about costly redesigns. As a result, designers must consider the effects of interconnects at the early stages of the design cycle.
Researchers have presented some methods, such as the Computer Aided Design (CAD) tools and Simulation Program with Integrated Circuit Emphasis (SPICE) to analyze on-chip interconnect. However, these simulation tools need a rather long time to obtain the estimated results and presents higher requirements for data storage, which limits their application in practice. To solve the problems existing in simulation tools, researchers presented some analytic formulas, such as the Elmore-based models, to reduce calculation time. However, such models are not accurate enough when characterizing the high speed on-chip interconnects.
Considering the difficulties existing in current methods and needs for new methods, this thesis proposes a new analytic method based on the numerical inversion of the Laplace transform (NILT) to estimate the behavior of the on-chip interconnect in time domain. Compared to the existing methods, the proposed method can provide accurate and efficient estimations for electrically long interconnect line and for input signals with very sharper rise time, which describes how long the input signal spends in the intermediate state between two valid logic levels. Numerical examples verify the accuracy and efficiency of the proposed method when comparing to two popularly existing methods.
Jiang, Yu, "Analytic Delay Model of RLC Interconnects using Numerical Inversion of the Laplace Transform" (2020). Electronic Thesis and Dissertation Repository. 7125.