Date of Award
2007
Degree Type
Thesis
Degree Name
Master of Engineering Science
Program
Electrical and Computer Engineering
Supervisor
Prof. Arash Reyhani-Masoleh
Abstract
The Advanced Encryption Standard (AES) is the newly accepted private-key cryp tographic standard for transferring block of data securely. However, the faults that accidently or maliciously occur in the hardware implementation of this standard may cause erroneous encrypted/decrypted output that results in losing the original mes sage and/or leaking the secret key information. In this thesis, parity-based concurrent fault detection schemes for designing high performance architectures of the AES are presented. For high performance appli cations, using look-up tables for implementing S-box and inverse S-box and their parity predictions is avoided. Instead, logic gate implementations based on compos ite fields are utilized. After analyzing the error propagation due to injecting random and all single faults, these structures have been divided into several blocks and closed formulations for parity predictions of them are obtained. In addition to considering the original S-boxes and inverse S-boxes and their fault detection schemes, modified structures are proposed and simulated and it is shown that they detect all single faults and almost all random faults. Moreover, the overhead costs, including space complexity and time delay of the proposed schemes are analyzed and compared with their counterparts. Finally, the implementation results for the proposed fault detection schemes are presented.
Recommended Citation
Mozaffari Kermani, Mehran, "Fault Detection Schemes for High Performance VLSI Implementations of the Advanced Encryption Standard" (2007). Digitized Theses. 5106.
https://ir.lib.uwo.ca/digitizedtheses/5106