Date of Award
Doctor of Philosophy
Complementary Metal Oxide Silicon (CMOS) technology has been the fastest growing fabrication process for the Very Large Scale Integrated (VLSI) circuits in the last few years, and long term predictions confirm its future importance. The minimum CMOS feature size is presently about one micron and it is certain that feature dimensions will reach the submicron range in mid nineties.;Smaller dimensions yield advantages, namely greater speed, higher device complexity and performance, and disadvantages such as greater susceptibility to electrical damage. During the past few years, the reliability of CMOS integrated circuits has received much attention, matched by publications on the subject. Higher reliability hardened integrated circuits have been developed as a response to demands for simplified shielding and demands for more reliable systems operating in hostile environments. The key step in developing hardened integrated circuits is the study of the mechanisms that make them fail. By understanding the failure conditions one can design more reliable components, select more suitable materials, and improve in-process control and screening. Also, it allows to develop test patterns, or accelerated test strategies for the evaluation of the integrated circuits susceptibility to damage.;In this study, a series of measurements were performed on a variety of custom fabricated CMOS Charge-Coupled Devices (CCDs) and dedicated modular test structures to investigate the latent model of failure due to Electrostatic Discharge (ESD). Test devices were stressed using the current injection method and measurements of the quiescent current were used to detect the failure thresholds. The fault sites were further isolated and the failure mechanisms studied by measuring the electrical characteristics before and after thermal and optical interaction. The measurements of oxide trapped charge was performed using the capacitance-voltage profiles. A model was proposed to explain the observed phenomena, based on charge injection and trapping in the gate oxide. The experimental methods developed for locating, measuring and analysis of the failure sites have been found sufficiently robust to be generally useful.
Chum, Kenneth, "Experimental Study Of Cmos Structures: Design For Reliability In Hostile Environments" (1992). Digitized Theses. 2104.